Comprehensive knowledge of executing verification tasks for IP/Subsystem/SoC verification, GLS, Formal Verification, Validation, and Emulation, from Test design to Coverage close.
ASIC/ RTL Design
Completing IP/SoC projects related to RTL design, architecture, microarchitecture, synthesis, and SoC integration. configuring Spyglass UPF, Lint, and CDC flows for clients.
FGPA Design
Expertise in Xilinx, Altera, and Microchip platforms for Prototyping and Validation of FPGA-targeted RTL Design, High-Level Synthesis, Timing Analysis, IP Development, and Integration.
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